1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus formed on a semiconductor.
2. Related Background Art
Several types of conventional photoelectric conversion apparatuses whose photoelectric conversion pixels have output lines are available. These photoelectric conversion apparatuses are classified into MOS, SIT, FET, CMD, and bipolar photoelectric conversion apparatuses in accordance with different pixel arrangements.
FIG. 1 shows a two-dimensional bipolar photoelectric conversion apparatus in which each pixel is formed of a bipolar transistor to accumulate photocarriers in the base region.
Referring to FIG. 1, each photoelectric conversion pixel 1 is composed of an npn bipolar transistor 2, a p-type MOS transistor 3 connected to the base of the npn bipolar transistor 2 to reset the base, and a pixel capacitance 4 for controlling the potential of the base. A pixel accumulation signal output line 5 is connected to the emitter of the corresponding bipolar transistor 2. A MOS transistor 6 resets the corresponding output line 5. A transfer capacitance 7 holds and transfers an output voltage of the corresponding photoelectric conversion pixel 1. A MOS transistor 8 switches between the corresponding output line 5 and the corresponding accumulation capacitance 7. A signal from the transfer accumulation capacitance 7 is transferred to a horizontal output line 9. A MOS transistor 10 switches between the corresponding accumulation capacitance 7 and the horizontal output line in accordance with an output from a horizontal shift register 33. A preamplifier 11 amplifies a signal appearing on the horizontal output line 9. The preamplifier 11 has an output terminal 12.
A MOS transistor 13 resets the horizontal output line 9. A drive line 14 drives the corresponding pixels. A MOS transistor 16 switches between the corresponding drive line 14 and a drive pulse input line 15 which is a vertical line selected in accordance with an output from a vertical shift register 34. The photoelectric conversion apparatus has a power supply terminal 17 of a reference potential V.sub.VC. An input terminal 18 applies a pulse .phi.VC to the gates of the MOS transistors 6. An input terminal 19 applies a pulse .phi.T to the gates of the MOS transistors 8. An input terminal 20 applies a pulse .phi.HC to the gate of the MOS transistor 13. An input terminal 21 receives a drive pulse .phi.R.
Referring to FIG. 1, for descriptive convenience, an area sensor having 2.times.2 photoelectric conversion pixels is illustrated. Outputs from the vertical shift register are represented by V1 and V2, and outputs from the horizontal shift register are represented by H1 and H2. In practice, 256.times.256 or more pixels are often arranged in the photoelectric conversion apparatus.
FIG. 2 is a pulse timing chart for explaining the operation of the two-dimensional photoelectric conversion apparatus shown in FIG. 1. Each pulse in FIG. 2 is represented by high level or low level. However, the drive pulse .phi.R has the reference potential V.sub.VC as an intermediate level.
When the output V1 from the vertical shift register 34 goes high, and the drive pulse .phi.R from the input terminal 21 goes high, the first row of the two-dimensional photoelectric conversion pixels is driven. In the photoelectric conversion pixel 1, the p-type MOS transistor (to be referred to as a PMOS hereinafter) 3 is kept off, while the base potential of the bipolar transistor 2 rises through the pixel capacitance 4. An emitter current flows, and a signal voltage accumulated in the base of the pixel appears on the corresponding output line 5 in the floating state because the pulse .phi.VC is kept low. Both the outputs H1 and H2 from the horizontal shift register 33 are kept low, and the pulse .phi.T is kept high. In this state, an output signal on the floating signal output terminal 5 is accumulated in the accumulation capacitance 7. Subsequently, when the outputs H1 and H2 from the horizontal shift register 33 go high to output the carriers in the accumulation capacitance 7 from the output terminal 12 through the output line 9 and the preamplifier 11. Note that when the output H1 goes high to set the column of the output H1 in a drive state, and the accumulation capacitance 7 is discharged, the output H1 goes low, and the pulse .phi.HC goes high. The signal line 9 is reset. The column of the output H2 is then set in the drive state to sequentially read out the carrier signals from the signal line 9.
In the pixels of each row, when the vertical shift register output V1 is kept high, and the drive pulse .phi.R goes low, the PMOSs 3 are turned on to set the base potential of the bipolar transistors 2 to the reference potential V.sub.VC. When the pulse .phi.VC goes high, and the MOS transistors 6 are turned on to set and fix the signal output lines 5 to the reference potential V.sub.VC, the drive pulse .phi.R goes high. In this state, the PMOSs 3 are turned off, and the bipolar transistors 2 of the first row are turned off to cause the emitter and base currents to flow. The base potential of the bipolar transistors 2 gradually drops to about V.sub.VC +0.6 V within several micro seconds, thereby resetting the pixel capacitances 4. In this case, when the drive pulse .phi.R returns to the intermediate level V.sub.VC, the base potential is lowered through the pixel capacitances 4, and these transistors are reverse-biased with respect to the emitter potential V.sub.VC. When the output V1 goes low, driving of this row is completed. The pixels of the first row start an accumulation operation for accumulating the optical carriers in the base regions until the first row is selected again.
When the output V2 goes high to select and drive the second row, the carrier signals are output. An operation for resetting the pixels is the same as in the first row.
In the bipolar photoelectric conversion apparatus described above, a signal voltage accumulated in the pixel capacitance almost defined by each pixel capacitance 4 directly appears on the corresponding accumulation capacitance 7. When the accumulation capacitance 7 is much larger than the pixel capacitance 4, the signal charge is amplified by a ratio of the two capacitance. Therefore, the influences of noise from the signal output path, the output line 5, the accumulation capacitance 7, the output line 9, and the preamplifier 11 can be reduced.
In the conventional example, however, when the signal is transferred from the accumulation capacitance 7 to the horizontal output line 9 in FIG. 1, the signal is capacitively divided by the stray capacitance of the horizontal output line 9, thereby lowering the signal potential. Even in a dark state, a dark output varies depending on the variations in characteristics of each pixel, and the S/N ratio is undesirably lowered. In particular, when the bipolar transistor is used for the light-receiving pixel as in the conventional example shown in FIG. 1, the accumulation capacitance 7 often has a large value. When the emitter flows to charge the accumulation capacitance 7 in reading out the signal from the pixel, the signal charge in the pixel base is destroyed. An increase in destruction amount causes an increase in noise, thereby greatly reducing the S/N ratio.
In addition, a general conventional photoelectric conversion pixel has a simple photoelectric conversion function of reset.fwdarw.accumulation.fwdarw.read-out. Signal processing for the pixel output must be performed in an area except for the photoelectric conversion pixel. This photoelectric conversion pixel has a limitation which requires a field memory to process signals.
An example of a solid-state image pickup device of another type is shown in FIGS. 8 to 11. FIG. 8 is a diagram showing the overall circuit arrangement. Referring to FIG. 8, pixels 121-11 to 121-mn are formed on a single substrate in the matrix form. Each pixel comprises an n-channel normally on (depletion) SIT (Static Induction Transistor) 122 serving as an image pickup element, a gate capacitor 124 connected to a floating gate 123 of the SIT 122, a p-channel enhancement control transistor 125 having a source-drain path connected to the floating gate 123 (each pixel is represented by a broken line).
A video voltage V.sub.D is applied to the drain (substrate) of the SIT constituting each pixel. Row lines 126-1, . . . , 126-m are connected to the gate capacitors of the SITS of the pixels 121-11 to 121-1n, . . . , 121-m1 to 121-mn of the rows arranged in the X direction, and row selection signals .phi..sub.G1, . . . , .phi..sub.Gm are applied from a vertical scanning circuit (vertica shift register) 127 to the row lines 126-1, . . . , 126-m, respectively. Column lines 128-1, . . . , 128-n are connected to the sources of the SITs of pixels 121-11 to 121-m1, . . . , 121-1n to 121-mn of the columns arranged in the Y direction, respectively. These column lines are grounded through column selection transistors 129-1, . . . , 129-n, a common video line 130, and a load resistor 131, and column selection signals .phi..sub.S1, . . . , .phi..sub.Sn are applied from a horizontal scanning circuit (horizontal shift register) 132 to the gates of the column selection transistors 129-1, . . . , 129-n, respectively.
A control gate line 133 and an overflow drain line 134 are respectively connected to the gate and drain of the control transistor 125 constituting each pixel, and a control gate signal .phi..sub.c and a control drain voltage V.sub.c are applied to the control gate line 133 and the overflow drain line 134, respectively.
FIG. 9 is a plan view showing the arrangement constituted by four adjacent pixels. FIG. 10 is a sectional view of this arrangement along the line 10--10 of FIG. 9. In this arrangement, to increase the area efficiency of the pixels formed on a substrate 140, four adjacent pixels are formed symmetrically in the vertical and horizontal directions. The substrate 140 constitutes the drain of each SIT and consists of an n.sup.+ - or n-type semiconductor. An n.sup.- -type epitaxial layer 141 is grown on the substrate 140, and a separation region 142 consisting of a buried insulator or the like is formed in the epitaxial layer 141 to electrically and optically separate the adjacent pixels from each other. In each pixel, the gate and source of the SIT are constituted by a p.sup.+ -type diffusion layer 143 and an n.sup.30 -type diffusion layer 144 formed on the surface of the epitaxial layer 141, respectively. The n.sup.+ -type diffusion layer 144 is connected to the corresponding column lines 128-i and 128-(i+1) through a wiring layer 145 consisting of, e.g., polysilicon. Row line electrodes 146-i and 146-(i+1) consisting of, e.g., polysilicon and forming the row lines 126-i and 126-(i+1) through a gate oxide film are formed on the p.sup.+ -type diffusion layer 143, so that the row line electrode forms a gate capacitor at a portion opposing the p.sup.+ -type diffusion layer 143.
The p.sup.+ -type diffusion layer 143 of the respective pixels is formed to extend to the central portion of the four adjacent pixels. The central portion serves as the source of the control transistor 125 of each pixel. At the same time, a p.sup.+ -type diffusion layer 147 constituting the drains of the control transistors of the four pixels is formed on the epitaxial layer 141 at the central portion of the four pixels so as to be spaced apart from the p.sup.+ -type diffusion layer 143 constituting the gate of the SIT and the source of the control transistor of each pixel. The p.sup.+ -type diffusion layer 147 is connected to the overflow drain line 134 through a wiring electrode 148. A control gate electrode 149 of the control transistors of the four pixels which forms the control gate line 133 through the gate oxide film is commonly formed on the surface of the epitaxial layer 141 between the p.sup.+ -type diffusion layers 147 and 143.
An operation of the above arrangement will be described with reference to the timing chart shown in FIG. 11. In this arrangement, as described above, the row lines 126-1 to 126-m are sequentially selected. After each row line is selected, the column lines 128-1 to 128-n are sequentially selected. In accordance with this X-Y addressing scheme, pixel signals are sequentially read out. When a signal read-out period t.sub.H for each row line is completed, all the pixels of the selected row line are simultaneously reset during a horizontal blanking period t.sub.BL for selecting the next row line. In particular, the pixel 121-22 is taken as an example, and its operation will be described with reference to a change in its floating gate potential V.sub.G (2,2) in FIG. 11. In the potential V.sub.G (2,2) of the floating gate 123 of the pixel 121-22 in FIG. 11, a solid line represents a potential upon incidence of light during an image pickup operation, while a broken line represents a potential without incidence of light during the image pickup operation.
At a timing t.sub.1, when the row selection signal .phi..sub.G2 applied to the row line 126-2 has a voltage V.phi..sub.G, the potential of the floating gate of each SIT connected to this row line is increased by almost V.phi..sub.G. More specifically, the potential is increased by EQU {C.sub.G /(C.sub.J +C.sub.G)}.multidot.V.phi..sub.G
where C.sub.G is the capacitance of the gate capacitor 124, and C.sub.J is the parasitic diffusion capacitance of the p.sup.+ -type diffusion layer 143.
At a timing t.sub.2, when the column selection signal .phi..sub.S2 goes high, and the column line 128-2, i.e., the pixel 121-22 is selected, a signal current depending on the potential V.sub.G (2,2) of the floating gate 123 of the pixel 121-22 flows through the load resistor 131 through the column line 128-2, the column selection transistor 129-2, and the video line 130 and is read out as an output signal V.sub.OUT upon the voltage drop across the load resistor 131. In this signal read-out, the optical charge accumulated in the floating gate 123 is generally held, and this read-out is nondestructive read-out.
The selection of the last line 128-n is completed. At a timing t.sub.3 when the signal read-out of all the pixels 121-21 to 121-2n connected to the row line 126-2 is completed, i.e., at the start of the horizontal blanking period t.sub.LB, the voltage of the control gate signal .phi..sub.C applied to the control gate line 133 is set to -V.phi..sub.C for turning on the control transistor 125. At this time, the surface potential .phi..sub.S (0) under the control gate electrode 149 changes to .phi..sub.S (-V.phi..sub.C), and the gate potential V.sub.G (2,2) is forcibly clamped to the potential .phi..sub.S (-V.phi..sub.C), thereby resetting the gate potential. In the subsequent light irradiation, the optical charge Q.sub.P accumulated in the gate is swept. The voltage -V.phi..sub.C of the control gate signal .phi..sub.C is set such that the surface potential .phi..sub.S (-V.phi..sub.C) under the control gate electrode 149 upon application of the control gate signal .phi..sub.C is almost equal to a pinch-off voltage V.sub.GO of the SIT, and condition .phi..sub.S (-V.phi..sub.C)&gt;V.sub.C is established for the control drain voltage V.sub.C.
At a timing t.sub.4, i.e., at the end of the horizontal blanking period t.sub.BL, the row selection signal .phi..sub.G2 goes low, and the control gate signal .phi..sub.C is set zero. With this operation, the gate potential V.sub.G (2,2) is decreased to V.sub.G (2,2)=.phi..sub.S (-V.phi..sub.C)-V.phi..sub.G. The optical charge is integrated depending on the incident light amount during the image pickup period until the next read-out. For example, the gate potential is increased by, e.g., Q.sub.P /C.sub.G (=.DELTA.V.sub.GP).
In this arrangement, the control gate signal .phi..sub.C is applied not only to the electrodes of the control gate lines 133 of the pixels connected to the selected row line, but also to the electrodes of all the pixel control gate lines 133 which are set in a nonselected state. When the gate signal .phi..sub.C has the voltage -V.phi..sub.C, the surface potential under the electrode of the control gate line 133 of each nonselected pixel becomes almost equal to .phi..sub.S (-V.phi..sub.C), i.e., the pinch-off voltage V.sub.GO as in the selected pixels. For this reason, even if the optical charge accumulation amounts in some nonselected pixels are equal to each other, and an increase .DELTA.V.sub.GP of the gate electrodes becomes EQU .phi..sub.S (-V.phi..sub.C)-V.phi..sub.G .DELTA.V.sub.GP &gt;.phi..sub.S (-V.phi..sub.C)
that is, .DELTA.V.sub.GP &gt;V.phi..sub.G, the optical charge corresponding to the potential .phi..sub.S (-.phi.V.sub.C) i.e., the gate potential which exceeds the pinch-off voltage V.sub.GO of the SIT is swept to the overflow drain line 134 through the channel below the control gate electrode. In addition, the overflow operation of the excessive charge is performed for all the nonselected pixels every time the row line is changed. Even if strong incident light is present, the potential of the floating gate does not exceed the pinch-off voltage V.sub.GO. For this reason, a semi-selected signal phenomenon can be effectively prevented, and this can be equivalently observed in blooming control.
Each pixel is reset by causing the control gate signal .phi..sub.C to clamp the potential of the floating gate of the SIT to .phi..sub.S (-V.phi..sub.C). The residual optical charge in the resetting operation can be perfectly zero. Therefore, in forward-biasing and resetting a p-n junction between the gate and source of the SIT, various after image phenomena can be perfectly controlled in this arrangement.
The conventional example described above poses a problem of large fixed pattern noise (to be referred to as FPN hereinafter) as one of the drawbacks of an amplification solid-state image pickup element. In an application of this element to a light amount detector, a target object must be distinguished from external light and detected with high precision. A so-called external light removal function is required.
A conventional example shown in FIG. 12 is available to solve the above problem. The arrangement and operation of the lower half of FIG. 12 are identical to those in FIGS. 8 to 11. In the upper half of FIG. 12, a drive signal is supplied from a vertical scanning circuit 152 to horizontal drive lines 150-1 and 150-2 to activate the optical signals from memory cells 153-11 to 153-22 for each horizontal drive line. Each pixel signal read out onto the vertical output line is output to the horizontal output line for each pixel upon reception of timing pulses .phi..sub.S1 and .phi..sub.S2 from a horizontal scanning circuit 132. At this time, the read-out of each pixel and the read-out of each pixel of the lower half of FIG. 12 are simultaneously performed. Signals are simultaneously read out from the pixels 121-22 of the lower half and the pixel 153-22 of the upper half onto a vertical output line 128-2. When incident light components having the same light amount are supplied to the pixels, a double optical carrier component appears at an output V.sub.out. In this case, two identical image sensors, two optical systems for focusing outputs from the image sensors onto a chip, and two vertical scanning circuits are required. However, the optical sensitivity can be improved, and the FPN can be reduced.
In this conventional example, although the above problem can be solved and the FPN can be reduced, memory elements having the same number as that of pixels are required. For this reason, for an image pickup element for a high resolution, a chip size undesirably becomes very large.